Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements

ABSTRACT

The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer under test for testing and burn-in. The interconnections are formed in recesses sized and shaped to receive and contain approximately 10% to 50%, and preferably about 30%, of the total height of each solder ball within its associated interconnection. Such a design compensates for under-sized or misshapen solder balls on the die under test and thereby prevents a possible false failure indication for the die under test. This design also distributes the forces on the solder ball caused by biasing the die under test to its temporary package to the periphery of the solder ball and thus reduces the likelihood of damage to the solder ball or the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/848,762,filed May 18, 2004, which will issue as U.S. Pat. No. 7,126,224 on Oct.24, 2006, which is a continuation of application Ser. No. 10/310,257,filed Dec. 4, 2002, now U.S. Pat. No. 6,740,578, issued May 25, 2004,which is a divisional of application Ser. No. 09/649,225, filed Aug. 28,2000, now U.S. Pat. No. 6,599,822, issued Jul. 29, 2003, which is acontinuation of application Ser. No. 09/164,113, filed Sep. 30, 1998,now U.S. Pat. No. 6,214,716, issued Apr. 10, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for forming an interconnectionfor receiving bumps or balls of a semiconductor device for testing orburn-in of the device. In particular, the present invention relates to amethod for forming sloped-wall, metal-lined interconnections to receiveand contain portions of solder balls of a semiconductor device therein.

2. State of the Art

Integrated circuit devices are well-known in the prior art. Suchdevices, or so-called “semiconductor dice,” may include a large numberof active semiconductor components (such as diodes, transistors) incombination with (e.g., in one or more circuits) various passivecomponents (such as capacitors, resistors), all residing on a“semiconductor chip” or die of silicon or, less typically, galliumarsenide or indium phosphide. The combination of components results in asemiconductor or integrated circuit die that performs one or morespecific functions, such as a microprocessor die or a memory die, thelatter as exemplified by ROM, PROM, EPROM, EEPROM, DRAM and SRAM dice.

Such semiconductor dice are normally designed to be supported or carriedin an encapsulant or other package and normally have a plurality ofexternally accessible connection elements in the form of solder balls,pins, or leads, to which the circuits on each semiconductor die areelectrically connected within the package to access other electroniccomponents employed in combination with each semiconductor die. Bondpads on the active surface of a die may be directly in contact with theconnection elements, or connected thereto with intermediate elements,such as bond wires or TAB (Tape Automated Bonding, or flex circuit)connections, or rerouting traces extending to remote locations on thedie active surface. An encapsulant is usually a filled polymer compoundtransfer molded about the semiconductor die to provide mechanicalsupport and environmental protection for the semiconductor die, mayincorporate a heat sink in contact with the die, and is normally squareor rectangular in shape.

Bare semiconductor dice are usually tested at least for continuity, andoften more extensively, during the semiconductor die fabrication processand before packaging. Such more extensive testing may be, and has been,accomplished by placing a bare semiconductor die in a temporary packagehaving terminals aligned with the terminals (bond pads) of thesemiconductor die to provide electrical access to the circuits on thesemiconductor die and subjecting the semiconductor die via the assembledtemporary package to bum-in and discrete testing. Such temporarypackages may also be used to test entire semiconductor wafers prior tosingulating the semiconductor wafers into individual semiconductor dice.Exemplary state-of-the-art fixtures and temporary packages forsemiconductor die testing are disclosed in U.S. Pat. Nos. 5,367,253;5,519,332; 5,448,165; 5,475,317; 5,468,157; 5,468,158; 5,483,174;5,451,165; 5,479,105; 5,088,190; and 5,073,117. U.S. Pat. Nos. 5,367,253and 5,519,332, assigned to the assignee of the present application, areeach hereby incorporated herein for all purposes by this reference.

Discrete testing includes testing the semiconductor dice for speed andfor errors that may occur after fabrication and after bum-in. Bum-in isa reliability test of a semiconductor die to identify physical andelectrical defects that would cause the semiconductor die to fail toperform to specifications or to fail altogether before its normaloperational life cycle is reached. Thus, the semiconductor die issubjected to an initial heavy duty cycle that elicits latent silicondefects. Bum-in testing is usually conducted at elevated potentials andfor a prolonged period of time, typically 24 hours, at varying andreduced and elevated temperatures, such as −15° C. to 125° C., toaccelerate failure mechanisms. Semiconductor dice that survive discretetesting and bum-in are termed “known good die,” or “KGD.”

As noted above, such testing is generally performed on baresemiconductor dice. However, while desirable for saving the cost ofencapsulating bad semiconductor dice, testing bare, unpackagedsemiconductor dice requires a significant amount of handling of theserather fragile structures. The temporary package must not only becompatible with test and bum-in procedures, but must also physicallysecure and electrically access the semiconductor die without damagingthe semiconductor die. Similarly, alignment and assembly of asemiconductor die within the temporary package and disassembly aftertesting must be effected without semiconductor die damage. The smallsize of the semiconductor die itself and minute pitch (spacing) of thebond pads of the semiconductor die, as well as the fragile nature of thethin bond pads and the thin protective layer covering devices andcircuit elements on the active surface of the semiconductor die, makethis somewhat complex task extremely delicate. Performing theseoperations at high speeds with requisite accuracy and repeatability hasproven beyond the capabilities of most state of the art equipment. Thus,since the encapsulant of a finished semiconductor die providesmechanical support and protection for the semiconductor die, in someinstances, it is preferable to test and bum-in semiconductor dice afterencapsulation.

A common finished semiconductor die package design is a flip-chipdesign. A flip-chip semiconductor design comprises a pattern or array ofterminations (e.g., bond pads or rerouting trace ends) spaced about anactive surface of the semiconductor die for face-down mounting of thesemiconductor die to a carrier substrate (such as a printed circuitboard, FR4 board, ceramic substrate, or the like). Each termination hasa minute solder ball or other conductive connection element disposedthereon for making a connection to a trace end or terminal on thecarrier substrate. This arrangement of connection elements is usuallyreferred to as a Ball Grid Array or “BGA.” The flip-chip is attached tothe substrate trace ends or terminals, which are arranged in amirror-image of the BGA, by aligning the BGA thereover and (if solderballs are used) refluxing the solder balls for simultaneous permanentattachment and electrical communication of the semiconductor die to thecarrier substrate conductors.

Such flip-chips may be tested and/or burned-in prior to their permanentconnection to a carrier substrate by placing each flip-chip in atemporary package, such as those discussed above. As shown in FIG. 31,each solder ball 304 attached to a bond pad 302 of aflip-chip-configured die 300 is in physical contact with a conductivetrace 306 on a contact wall 308 of the temporary package. The conductivetraces 306 transmit electrical signals to the die 300 for testing orburn-in. With such a temporary package, each solder ball 304 contactseach conductive trace 306 at only one contact point 310. With only onecontact point 310 per solder ball 304, all of the stresses caused bybiasing the die 300 to the contact wall 308 of the temporary package areconcentrated on the one contact point 310 on each solder ball 304. Thesestresses can result in the solder balls 304 fracturing, dislodging fromthe bond pad 302, or otherwise damaging the flip-chip-configured die300.

Furthermore, such a temporary package configuration is also insensitiveto ensuring electrical connection to the temporary package ofnon-spherical/irregularly shaped solder balls, or different sized balls,in the BGA. FIG. 32 illustrates an under-sized solder ball 312 in thearrangement similar to that shown in FIG. 31. Elements common betweenFIG. 31 and FIG. 32 retain the same designation. The under-sized solderball 312 does not make contact with the conductive trace 306. This cangive a false failure indication for the flip-chip-configured die 300,when, in reality, it could be “good” when an adequate connection isachieved when the under-sized solder ball 312 is refluxed for permanentattachment to a carrier substrate. At the least, the die in question isinitially rejected and must be retested to verify the source of theapparent failure.

Therefore, it would be advantageous to develop improved methods andapparatus for use with flip-chip-retaining temporary packages, whereinthe temporary packages can compensate for irregular solder ball shapeand size, and reduce the risk of damage to the semiconductor deviceunder test.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a method of forming interconnectionsfor a temporary contact with a semiconductor die, wafer or partialwafer, wherein the interconnections are capable of receiving solderballs for testing and bum-in. The present invention can be used for bothwafer level and chip level testing and bum-in, and other probe cardtechnology employing silicon inserts, as well as silicon KGD inserts.

The interconnections are designed to be formed in a recess, preferably asloped-wall (either smooth or “stepped”) via. Such an interconnectiondesign compensates for under-sized or misshapen solder balls on the dieunder test to prevent a possible false failure indication for the dieunder test and reduces and reorients the stress on each solder ball whenphysical contact is made to its mating interconnection.

The inventive interconnections are preferably formed by etching the viain a passivation layer that is applied over an active surface of asemiconductor substrate, such as a silicon wafer, a partial wafer thesame size or larger than a semiconductor die, or the like. The via maybe etched to expose a conductive trace under or within the passivationlayer. Alternatively, the conductive trace may be formed after the viais formed, wherein the conductive trace is formed on the exposed surfaceof the passivation layer and extends into the via. A metal layer,preferably of an oxidation-resistant metal such as gold, platinum,palladium, or tungsten, is formed in the via to contact the associatedconductive trace and complete the formation of the interconnection.

The interconnection is preferably circular, as viewed from above, toreceive the spherical solder ball, which protrudes partially within theinterconnect when placed in contact therewith. Preferably, approximately10% to 50% of the total height of the solder ball, and preferably about30% of the total height, will reside within the interconnect. With aspherical solder ball in a smooth sloped-wall via interconnection, eachsolder ball will make a circular, or at least arcuate, line of contactwith the interconnect surface about a periphery of the solder ball,rather than a single contact point. The circular contact distributes theforce on the solder ball when the semiconductor substrate is biasedagainst the insert carrying the interconnection in the temporarypackage, making damage to the solder ball or underlying bond pad lesslikely. Further, any oxide layer formed on the exterior surface of thesolder ball will be more easily penetrated by the line of contact thanthrough a single contact point effected with prior art interconnections.

With a solder ball received in a stepped-wall interconnection accordingto the invention, the solder ball may make multiple circular or at leastarcuate contacts with the edges of the steps of the steppedinterconnection, again facilitating electrical communication andpiercing any oxide layer on the solder ball. Such multiple arcuatecontacts further distribute the force applied to the solder ball duringpackage assembly and subsequent testing.

In one embodiment of the invention, multiple passivation and tracelayers are employed to accommodate small-pitched connection elementarrays having as many as a thousand or more inputs and outputs (I/Os).

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIGS. 1-9 are side cross-sectional views of a method of forming aninterconnection of the present invention;

FIG. 10 illustrates a solder ball of a die on a substrate, such as asilicon test package insert, residing in one embodiment of aninterconnection of the present invention;

FIG. 11 illustrates an under-sized solder ball and a misshapen solderball of a die on a substrate, such as a silicon test package insert,residing in interconnections of the present invention;

FIGS. 12-25 are side cross-sectional views of another method of formingan interconnection of the present invention;

FIG. 26 illustrates a solder ball of a die on a substrate, such as asilicon test package insert, residing in another embodiment of aninterconnection of the present invention;

FIG. 27 illustrates a small solder ball and a misshapen solder ball of adie on a substrate, such as a silicon test package insert, residing ininterconnections of the present invention;

FIG. 28 is a side cross-sectional view of an alternative conductivetrace configuration for the interconnection of the present invention;

FIG. 29 is a side cross-sectional view of a multi-layer traceconfiguration for the interconnections of the present invention;

FIG. 30 illustrates a solder ball on a substrate residing in yet anotherembodiment of an interconnection of the present invention;

FIG. 31 is a side cross-sectional view of a prior art temporary packagewith solder balls of a die in contact therewith; and

FIG. 32 is a side cross-sectional view of a prior art temporary packagewith two solder balls of a die, one under-sized disposed thereagainst.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1-9 illustrate side cross-sectional views of a method of forming asingle interconnection of the present invention, although typicallyhundreds, if not thousands, of such interconnections may besimultaneously fabricated on a single substrate. It should be understoodthat the figures presented in conjunction with this description are notmeant to be illustrations of actual cross-sectional views of anyparticular portion of an actual semiconductor device, but are merelyidealized representations that are employed to more clearly and fullydepict the process of the invention than would otherwise be possible. Itshould also be understood that the figures herein are not meant to be toscale nor otherwise in specific proportion, nor should they be so taken.

FIG. 1 illustrates a conductive trace 104, preferably of copper, formedon a dielectric layer 102 (preferably thermally grown SiO₂), whichresides on a semiconductor substrate, such as a silicon wafer 100. Abulk silicon structure, such as a silicon-on-sapphire (SOS) structure, asilicon-on-glass (SOG) structure, or other silicon-on-insulator (SOI)structure, may also be employed. By employing silicon at least as theexposed substrate layer supporting interconnections according to theinvention, the coefficient of thermal expansion (CTE) is matched withthat of the silicon semiconductor die, partial wafer or wafer undertest, a significant feature given the wide temperature swingsexperienced by the die and substrate bearing the inventiveinterconnections during bum-in. Thus, thermally induced stresses on thesolder balls of a flip-chip-configured die, partial wafer or wafer areminimized.

The conductive trace 104 contacts external circuitry of the package base(not shown) through TAB tape, wire bonds, or other conductivestructures, which transmit appropriate electrical signals for bum-in,testing, or the like. A passivation film 106 is formed over thedielectric layer 102, as well as the conductive trace 104, as shown inFIG. 2. The passivation film 106 is preferably a polyimide film or otherthick resin with a thickness of about 0.8 to 1 mil, or 20 to 25 microns,if a nominal 3 mil, or 75 micron, solder ball is to be contacted, aswill be explained below. If the ball size is enlarged, for example, toabout 13 mil or 325 microns, then the thickness of this film should bechanged accordingly to about 4 mil, or 100 microns. While otherpassivation materials such as silicon nitride, borophosphosilicate glass(BPSG), phosphosilicate glass (PSG) or borosilicate glass (BSG) may beemployed, polyimide is preferred as it exhibits a lower ε than the othermaterials, resulting in reduced capacitance in the structure, includingthe interconnection and associated traces and faster signal transmissionalong the copper conductive traces. A layer of etchant-resistivephotoresist film 108 is then applied over the passivation film 106, asshown in FIG. 3. The photoresist film 108 is then masked, exposed, andstripped to form a desired opening 112, preferably circular, in thephotoresist film 108, as shown in FIG. 4. The passivation film 106 isthen etched through the opening 112 in photoresist film 108 to form avia 114 with either sloped edges or walls 118 (preferably by facetetching) or straight (vertical) walls if desired, and which exposes aface surface 116 of the conductive trace 104, as shown in FIG. 5. Thephotoresist film 108 is then stripped, as shown in FIG. 6.

As shown in FIG. 7, a metal layer 120, preferably a metal such as gold,platinum, palladium, tungsten, or the like, to prevent oxidation of theexposed interconnection surface, is applied over the passivation film106, as well as in the via 114, by chemical vapor deposition (CVD),plasma-enhanced chemical vapor deposition (PECVD), physical vapordeposition (PVD) (sputtering or evaporation), or the like. The metallayer 120 may also be comprised of superimposed metal layers, such aschromium, copper, chromium-copper alloy, titanium, or the like, toeffect a better metallurgical connection to conductive trace 104, with anoble metal outer layer for contact with the solder ball.

A layer of etchant-resistive photoresist film is applied over metallayer 120 and is then masked, exposed, and stripped to form anetchant-resistive block 122 over the via 114, as shown in FIG. 8. Themetal layer 120 surrounding the via 114 is then etched down to thesurface of passivation film 106 and the etchant-resistive block 122 isstripped to form a discrete interconnection 124, as shown in FIG. 9. Thediscrete interconnection 124, for example, receives a solder ball 126(typically a 95%:5% or 63%:37% lead/tin solder ball), which is attachedto a bond pad 130 of a semiconductor element 128, such as a die, partialwafer or wafer, as shown in FIG. 10. The discrete interconnection 124 issized in combination with the slope of the walls of the sloped-wall via114 as shown and the depth or thickness of the passivation film 106through which via 114 is etched to receive therein approximately 10% to50%, and preferably about 30%, of the overall height of the solder ball126. In other words, the height 132 within the discrete interconnection124 is approximately 10% to 50%, and preferably about 30%, of theoverall height 134 of the solder ball 126. The solder ball 126preferably makes contact with the discrete interconnection 124 at acontact line 136 at least partially circling the solder ball 126. Theshape of the discrete interconnection 124 allows under-sized solderballs 138 and misshapen solder balls 140, which are attached to bondpads 130 of semiconductor element 128, to still make adequate electricalcontact with the discrete interconnection 124, as shown in FIG. 11.Moreover, thermally induced fatigue, which can result in solder ballbreakage, is lessened due to the enhanced contact area.

FIGS. 12-25 illustrate an alternative method of forming aninterconnection of the present invention. FIG. 12 illustrates aconductive trace 146 (again, preferably of copper) formed on adielectric layer 144 (again, preferably of a thermally grown oxide),which resides on a semiconductor substrate 142. The conductive trace 146contacts external circuitry (not shown) that transmits appropriateelectrical signals for burn-in, testing, or the like. A passivation film148, preferably a polyimide film, is formed over the dielectric layer144, as well as the conductive trace 146, as shown in FIG. 13. A layerof etchant-resistive photoresist film 150 is then applied over thepassivation film 148 and is then masked, exposed, and stripped to form adesired opening 152, preferably circular, in the photoresist film 150,as shown in FIG. 14. The passivation film 148 is then etched through theopening 152 in photoresist film 150 to a predetermined depth to form afirst via portion 154 into the passivation film 148, as shown in FIG.15. A first layer of silicon dioxide 156 is deposited over thephotoresist film 150 and an exposed portion of the passivation film 148,as shown in FIG. 16. The first layer of silicon dioxide 156 is thenetched, preferably spacer etched, to form a first lip 158 of silicondioxide in the corners 160 of the first via portion 154 and to expose aportion of the passivation film 148 in the first via portion 154, asshown in FIG. 17.

As shown in FIG. 18, the passivation film 148 is again etched to apredetermined depth to form a second via portion 162. A second layer ofsilicon dioxide 164 is deposited over the photoresist film 150, thefirst lip 158, and an exposed portion of the passivation film 148, asshown in FIG. 19. The second layer of silicon dioxide 164 is then etchedto form a second lip 166 of silicon dioxide in the corners 168 of thesecond via portion 162 and to expose a portion of the passivation film148 in the second via portion 162, as shown in FIG. 20. The passivationfilm 148 is again etched to a predetermined depth to form a third viaportion 170, as shown in FIG. 21.

This process is repeated until the step-by-step etching of thepassivation film 148 results in the exposure of the conductive trace146, wherein the photoresist film 150 and the lips (i.e., 158, 166, andothers formed thereafter) are removed, resulting in the stepped via 172shown in FIG. 22.

As shown in FIG. 23, a metal layer 174 is applied over the passivationfilm 148, as well as over and into the stepped via 172. A layer ofetchant-resistive photoresist film is applied over metal layer 174 andis then masked, exposed, and stripped to form an etchant-resistive block176 over the stepped via 172, as shown in FIG. 24. The metal layer 174surrounding the stepped via 172 is then etched and the etchant-resistiveblock 176 is stripped to form a discrete interconnection 178, as shownin FIG. 25. The discrete interconnection 178, for example, receives asolder ball 180, which is attached to a bond pad 184 of a semiconductorelement 186, such as a die, partial wafer or wafer, as shown in FIG. 26.The discrete interconnection 178 is designed to receive approximately10% to 50%, and preferably about 30%, of the overall height of thesolder ball 180. In other words, the solder ball height segment 188,protruding within the discrete interconnection 178, is approximately 10%to 50%, and preferably about 30%, of the overall height 190 of thesolder ball 180.

The discrete interconnection 178 has a staggered surface, which maycontact the solder ball 180 at several contact lines 192 circling orpartially circling the solder ball 180. The shape of the discreteinterconnection 178 allows small solder balls 194 and misshapen solderballs 196, which are attached to bond pads 184 of semiconductor element186, to still make extensive electrical contact with the discreteinterconnection 178, as shown in FIG. 27.

It is, of course, understood that the conductive traces such as 104, 146need not necessarily be buried under the passivation films 106, 148.FIG. 28 shows an alternative conductive trace configuration 200. Thealternative conductive trace configuration 200 comprises a substrate 202with a passivation film 206 formed over a dielectric layer 204. A via207 is formed in the passivation film 206 as discussed above. Theconductive trace 208 is then formed over the passivation film 206 andinto the via 207. A discrete interconnection 210, such as a layer ofgold or other oxidation-resistant metal, is formed on the portion ofconductive trace 208 lying within the via 207.

The present invention may also be applied to multi-layer conductivetrace configurations, as shown in FIG. 29. The multi-layer conductivetrace configuration 212 comprises a substrate 214 with a dielectriclayer 216 thereof. A lower conductive trace 218 is formed over thedielectric layer 216. A lower passivation layer 220 is formed over thelower conductive trace 218 and the dielectric layer 216. An upperconductive trace 222 is formed on the lower passivation layer 220 and anupper passivation layer 224 is formed over the upper conductive trace222 and the lower passivation layer 220. Discrete interconnections 226and 228 are formed in a manner discussed above to contact the upperconductive trace 222 and the lower conductive trace 218, respectively.The discrete interconnection 228 contacts the lower conductive trace 218through a conductive column 230 extending through the lower passivationlayer 220. It will be understood that such a structure may include threeor more trace layers in lieu of the two shown, so as to accommodate alarge number of discrete interconnections such as 226 and 228 at a smallpitch so as to accommodate one of the aforementioned thousand-plus I/Osemiconductor dice.

FIG. 30 illustrates yet another embodiment of the interconnect of thepresent invention. Elements common to FIG. 10 and FIG. 30 retain thesame numeric designation. The discrete interconnection 232 is formed byetching the substantially vertical walls for the via rather than slopedwalls, but is otherwise formed in a similar method to that described andillustrated in FIGS. 1-9. The discrete interconnection 232 receives asolder ball 126 that is attached to a bond pad 130 of a semiconductorelement 128, such as a die or wafer, as shown in FIG. 30. The discreteinterconnection 232 is also sized in diameter to receive approximately10% to 50%, and preferably about 30%, of the overall height of thesolder ball 126. In other words, the height 132 received within thediscrete interconnection 232 is approximately 10% to 50%, and preferablyabout 30%, of the overall height 134 of the solder ball 126.

Although the present disclosure focuses on testing flip-chip-configuredsingulated dice, it is, of course, understood that this technology canbe applied on a wafer or partial-wafer scale.

Having thus described in detail certain preferred embodiments of thepresent invention, it is to be understood that the invention defined bythe appended claims is not to be limited by particular details set forthin the above description, as many additions, deletions and modificationsthereto are possible without departing from the scope thereof.

1-12. (canceled)
 13. A method of fabricating an interconnectionstructure on a substrate, the method comprising: etching a via to aselected size and shape in a passivation layer disposed on a substrate;forming a conductive trace in communication with the via; and forming atleast one metal layer over a portion of the conductive trace within thevia, over walls thereof and over a periphery of the surface of thepassivation layer proximate the via to form an interconnection structureconfigured for receiving a portion of a substantially sphericalinterconnection element projecting from a surface of a semiconductordevice to a height, wherein the interconnection structure is dimensionedto receive the portion of the substantially spherical interconnectionelement to an extent of approximately 10% to 50% of the height thereof.14. The method of claim 13, wherein the interconnection structure isdimensioned to receive the portion of the substantially sphericalinterconnection element to an extent of approximately 30% of the heightthereof.
 15. The method of claim 13, wherein etching the via comprisesfacet etching to form a via having sloped walls.
 16. The method of claim13, wherein etching the via comprises successive masking and etchingsteps to form a via having stepped walls.
 17. The method of claim 13,further comprising forming a dielectric layer over the substrate,forming the passivation layer over the dielectric layer, and whereinetching the via in the passivation layer comprises etching the viathrough the passivation layer to proximate the dielectric layer.
 18. Themethod of claim 18, further comprising forming the conductive trace overthe dielectric layer prior to etching the via, and exposing a portion ofthe conductive trace by the etching.
 19. The method of claim 13, furthercomprising forming the conductive trace over the passivation layer andinto the via after etching thereof.
 20. An article for contacting atleast one interconnection element of at least one semiconductor device,the article comprising: a substrate having a passivation layer thereon;at least one conductive trace; and a metal-lined via comprising at leastone layer of metal extending through the passivation layer and inelectrical communication with the at least one conductive trace, whereinthe metal-lined via is sized and configured to receive, withoutdeformation, a substantially spherical interconnection elementprotruding to a height from at least one semiconductor device to a depthcorresponding to approximately 10% to 50% of the height of thesubstantially spherical interconnection element and establish anelectrical connection therewith at the depth by way of biased contact ofonly a portion of an interior surface of the metal-lined via with only aportion of an exterior surface of the substantially sphericalinterconnection element received therewithin.
 21. The article of claim20, wherein the metal-lined is configured of a size and shape to receiveapproximately 30% of the height of the substantially sphericalinterconnection element.
 22. The article of claim 20, wherein themetal-lined via includes sloped sidewalls.
 23. The article of claim 20,wherein the metal-lined via includes stepped sidewalls.
 24. The articleof claim 20, wherein the at least one conductive trace comprises copper.25. The article of claim 20, wherein the passivation layer comprisespolyimide.
 26. The article of claim 20, wherein the metal-lined viacomprises a metal from the group comprising gold, platinum, palladium,and tungsten.
 27. The article of claim 20, wherein the passivation layerhas a thickness of about 100 microns or less.
 28. The article of claim20, wherein the passivation layer has a thickness of about 20 to 25microns.
 29. The article of claim 20, wherein the at least oneconductive trace extends over the passivation layer and into the viaunder the at least one layer of metal.
 30. The article of claim 20,wherein the at least one conductive trace lies on a dielectric layerbetween the passivation layer and the substrate, and a portion thereofat a bottom of the via is in contact with the at least one layer ofmetal.
 31. The substrate of claim 30, wherein the dielectric layercomprises silicon dioxide.
 32. The article of claim 20, wherein themetal-lined via is sized and configured to establish the electricalconnection only along at least one contact line consisting of theportion of the interior surface of the metal-lined via at leastpartially circling the portion of the exterior surface of thesubstantially spherical interconnection element.